Conventional active matrix liquid crystal panels are constituted by two transparent substrates sandwiching a liquid crystal layer. One of the substrates is formed with a plurality of data signal lines (hereinafter may also called “source lines”) and a plurality of scanning signal lines (hereinafter may also called “gate lines”) crossing the data signal lines so as to provide a matrix of pixel formation portions each formed at one of the intersections. Each pixel formation portion includes a pixel electrode connected with one of the data signal lines that passes a corresponding intersection, via a TFT (Thin Film Transistor) which serves as a switching device. The TFT has its gate terminal connected to the scanning signal lines which passes the intersection. The other transparent substrate is formed with an electrode (hereinafter called “common electrode”) which is common to all of the pixel electrodes. Liquid crystal display devices which employ a panel configured as the above are provided with a drive circuit for causing the liquid crystal panel to display images. The drive circuit includes a scanning signal line drive circuit (also called “gate driver”) which applies scanning signals to the scanning signal lines for sequential selection of the scanning signal lines, and a data signal line drive circuit (also called “source driver”) which applies data signals to the data signal lines for sequential writing of data to the pixel formation portions in the liquid crystal panel.
In such a liquid crystal display device, images to be displayed are formed by the plurality of pixel formation portions disposed in a matrix pattern. Each pixel formation portion has a circuit configuration as shown in FIG. 11(A), and includes: a capacity Clc (called “liquid crystal capacity”) formed by a pixel electrode and a common electrode Ec which sandwich the liquid crystal layer; a capacity Cs (hereinafter called “supplementary capacity”) formed by the pixel electrode and a supplementary electrode Es; and a TFT 10 which has its drain terminal connected with the pixel electrode. The TFT 10 has its source terminal connected with a data signal line DLk which passes through an intersection CPjk that corresponds to the pixel formation portion, and its gate terminal connected with a scanning signal line GLj that passes through the intersection CPjk. It should be noted that a pixel capacity for holding a voltage which represents the pixel value of the image to be displayed is formed by the liquid crystal capacity Clc and the supplementary capacity Cs.
In such a liquid crystal display device as the above, a data signal Dk is supplied from a data signal line DLk to the pixel electrode via the TFT 10 in each pixel formation portion, whereby a voltage which represents the value of the pixel that corresponds to the pixel electrode is applied between each pixel electrode and its common electrode Ec as well as between the pixel electrode and its supplementary electrode Es, to charge the liquid crystal capacity Clc and the supplementary capacity Cs. The liquid crystal layer changes its optical transmittance in accordance with the charge voltage, thereby displaying the image on the liquid crystal panel.
Now, there is a problem known with such a liquid crystal display device as the above: When the liquid crystal display device is started and before forming an image on the pixel formation portions by sequentially selecting the scanning signal lines (i.e. before starting display), electric potential in the common electrode Ec and the supplementary electrode Es rises to a certain extent to charge the liquid crystal capacity Clc or the supplementary capacity Cs in accordance with an electric potential difference between these two electrodes (FIG. 11(B)), resulting in an unintended black screen (in a normally-white screen) or a white screen (in a normally-black screen).
Conventional art attempts to solve this problem as follows: Right before starting display, an activation signal represented by an ON voltage is applied to all of the scanning signal lines, thereby turning on the TFTs and discharging the accumulated electric charges from the liquid crystal capacities Clc and the supplementary capacities Cs via the data signal lines DLk (FIG. 11(C)) (See Patent Document 1 through 4 for example).
FIG. 12 is a signal waveform chart which shows a sequence of operations (hereinafter called “Display-ON sequence”) performed in the case as described above, from the time when a liquid crystal display device is turned on to the time when display is started. In this method, a Display-ON signal Son is generated as a signal which indicates a start of the Display-ON sequence, based on e.g. power-ON detection in the liquid crystal display devices. When the Display-ON signal Son becomes active (High level in the figure), an ON voltage (activation signal which turns ON the TFT) is applied in synchronization with the vertical synchronizing signal VSY to all of the scanning signal lines to select them (Time t1). Thereafter, an OFF voltage (deactivation signal which turns OFF the TFT) is applied to all of the scanning signal lines to deselect them all (Time t2) before beginning a normal scanning procedure. As described, according to the conventional art, an OFF voltage is applied to all of the scanning signal lines simultaneously when the scanning signal lines are switched from the Selected state to the Deselected state in the Display-ON sequence. The following is a list of documents which disclose techniques including the above that are related to the present invention:
[Patent Document 1] JP-A Hei 2-272490 Gazette
[Patent Document 2] JP-A 2001-272650 Gazette
[Patent Document 3] JP-A 2002-323875 Gazette
[Patent Document 4] JP-A 2003-295829 Gazette
[Patent Document 5] JP-A Hei 6-160806 Gazette